1. Field of the Disclosure
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming a tri-gate FinFET device and the resulting device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 3A is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 102 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 100 includes three illustrative fins 104, a gate structure 106, sidewall spacers 108 and a gate cap 110. The gate structure 106 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 100. The fins 104 have a three-dimensional configuration: a height 104H, a width 104W and an axial length 104L. The axial length 104L corresponds to the direction of current travel, i.e., the gate length (GL) of the device 100 when it is operational. The portions of the fins 104 covered by the gate structure 106 is the channel region of the FinFET device 100. In a conventional process flow, the portions of the fins 104 that are positioned outside of the spacers 108, i.e., in the source/drain regions of the device 100, may be increased in size or even merged together (a situation not shown in FIG. 3A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins 104 in the source/drain regions of the device 100 is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. Even if an epi “merger” process is not performed, an epi growth process will typically be performed on the fins 100 to increase their physical size.
FIG. 3B depicts a simplistic plan view of the traditional FinFET device comprised of three illustrative fins 104. A cross-sectional view of the device 100 taken through the gate structure 106 is depicted in FIG. 3C. With reference to FIG. 3C, the device 100 includes a layer of insulating material 112 positioned between the fins 104, another layer of insulating material 114 that is positioned above the gate cap layer 110 and a gate contact structure 116 that is conductively coupled to the gate structure 106. The device 100 depicted in FIG. 3C is a tri-gate (or triple gate) FinFET device. That is, during operation, a very shallow conductive region 118 (shown only on the middle fin in FIG. 3C) will be established that provides a path or channel for current to flow from the source region to the drain region. The conductive region 108 forms inward of the side surfaces 104S and below the top surface 104T of the fins 104. As depicted in FIGS. 3B and 3C, the overall gate length (GL) of the FinFET device 100 and the overall gate width (GW) of the FinFET device 100 are all oriented in a direction that is substantially parallel to a horizontal surface 102A of the substrate 102.
While the traditional FinFET devices described above have significant advantages as compared to traditional planar devices, further improvement in such FinFET devices need to be made. For example, traditional FinFET devices still consume a significant amount of valuable plot space on a semiconductor substrate. Reducing the “foot-print” of such devices is becoming ever more difficult to achieve by simply reducing the critical dimensions of the various features of the device, e.g., the gate structure 106, the fin width 104W, etc. FIG. 4 is an illustrative example of a prior art logic device that is made by forming a plurality of traditional FinFET devices. More specifically, the logic device is comprised of a 4-fin P-type FinFET device, a 2-fin P-type FinFET device, a 6-fin N-type FinFET device and a 3-fin N-type FinFET device. Various gate structures, gate contacts and trench silicide source/drain contact structures are also depicted. In general, such an arrangement has a relatively large “foot-print” and results in some wasted space. Note the space between the 2-fin P-type FinFET device and the 3-fin N-type FinFET device. What is needed is a fundamentally new FinFET architecture that will reduce the footprint of a FinFET device and thereby reduce the footprint of integrated circuits that use such FinFET devices.
The present disclosure is directed to methods of forming a tri-gate FinFET device and the resulting device that may solve or reduce one or more of the problems identified above.